Flat panel displays in general, and liquid crystal displays in particular, are finding increasing use in data processing systems such as personal computing systems. These displays, which are driven by a video controller, provide a number of advantages over cathode ray tube type displays in terms of weight, size and compactness.
However, as is generally known, flat panel displays are chemically responsive systems, as opposed to electronically scanned systems, and thus suffer from several operational disadvantages in comparison with cathode ray tube type devices. Of particular importance, the chemical in a typical flat panel display can only maintain a visible image for a discrete time. Thus, as the size of the flat panel increases, a limiting display size is reached where an image being displayed will fade out unless it can be refreshed.
One solution to the size limitations facing flat panel displays is to use gangs of displays to provide the desired display size. For example, if the desired display area is 640.times.480, one solution is to use two displays of 640.times.240 in combination.
This use of multiple displays impacts other hardware in the data processing systems. In particular, the use of multiple panels creates a problem of how the video controller will drive the multiple displays. This problem is exacerbated when each display must have split screen display capability. The algorithms, calculations, and associated hardware adjustments required for a conventional controller to drive multiple displays with each having sophisticated display features are complicated and have not heretofore been satisfactorily resolved to applicants' knowledge.
The problems created can be more fully appreciated by reference to the following discussion taken in conjunction with FIGS. A and B. FIG. A is a stylized illustration of a memory 8 for driving a display 10 having a single panel according to the prior art. FIG. B is a stylized illustration of a memory 8 for driving a display 10 having dual panels 12 and 14 according to the prior art.
For a single panel display system such as the one shown in FIG. A, the address in memory 8 for line L on display 10, i.e., ADDR(L) is typically calculated as follows: EQU ADDR(L)=X +W*L if L.ltoreq.H, and EQU ADDR(L)=(L-(H+1))*W if L &gt;H
For a display system having an associated memory as shown in FIG. 1A, the address calculations would be started for L=1 and continued until L=480. The following logical steps could be employed in a conventional method for generating the addresses:
(1) Reset: every frame. PA1 (2) Initialize address =X. PA1 (3) Get the next line, set L=L+1. PA1 (4) Compare L to H. PA1 (5) If L.ltoreq.H, then add X to address. PA1 (6) If L &gt;H then address =0. PA1 (7) If L =FRAME, go to step (1). PA1 (8) Go to step (3). PA1 1. if H.sub.A &lt;240, & L.sub.1 .ltoreq.HA, ADDR(L.sub.1)=X+W* L.sub.1 ADDR(L.sub.2)=(240-HA+L.sub.2)*W PA1 2. if H.sub.A &lt;240, & L.sub.1 &gt;HA, ADDR(L.sub.1)=[L.sub.1 -(HA+1)]*W ADDR(L.sub.2)=[L.sub.2 -(HA+1)+240]*W PA1 3. if H.sub.A &gt;240, & L.sub.2 .ltoreq.(H.sub.A -240), ADDR(L.sub.1)=X+W*L.sub.1 ADDR(L.sub.2)=X+(L.sub.2 +240)*W PA1 4. if H.sub.A &gt;240, & L.sub.2 &gt;(H.sub.A -240), ADDR(L.sub.1)=X+W*L.sub.1 ADDR(L.sub.2)=[L.sub.2 -(H.sub.A +1)]*W+240
A conventional address generator embodying these logic steps may be employed to drive display 10. Such an address generator could be implemented using essentially an adder and a comparator.
The situation for a dual panel display system driven by a single address generator, as illustrated in FIG. 1B, is far more complicated. In order to use the dual panels as a single screen, two lines are displayed simultaneously, which requires calculation of the start address for both lines at the same time. For example, in a 480 line display, L.sub.1 and L.sub.2 will both vary from 1 to 240, and L.sub.1 will equal L.sub.2 to maintain sync. The address for line 1, ADDRL.sub.1, and the address for line 2, ADDRL.sub.2 will typically be calculated as follows:
It can be seen that as L.sub.1 and L.sub.2 vary between 1 and 240, there is no simple way to generate ADDR(L.sub.1) ADDR(L.sub.2). For example, a number of multipliers and comparators are required to implement the foregoing equations.
Prior art patents known to applicants have neither taught nor suggested any method or circuit for addressing the foregoing problems For example, U.S. Pat. No. 4,684,935 to Fujisaku, et al., discloses the use of dual memories for storing first (graphics) images and second (characters) images. A selection and combination circuit is used to display at either or both of two display units a combination of data from the image memories according to the display request The combination and selection circuits comprise signal mixing circuits. As another example, U.S. Pat. No. 4,651,146 to Lucaste et al., discloses the use of a multiple window display system for displaying data from different applications in a multi-tasking environment. U.S. Pat. No. 4,323,891 to Akashi describes a method and system for producing a cursor display signal in which display information is supplied to stations by using a mirror reflection. One cursor address is outputted while the cursor address for a divided screen is stored in a register in the controller.